Typically, many discrete piezoresistive elements are simultaneously made on a single silicon wafer. The wafer is then subdivided into the discrete devices. One or more resistors are diffused or implanted in each device area. Then, a web or diaphragm is usually provided in the wafer by etching each wafer location where a piezoresistive device is to be completed. Thereafter, metal electrodes are formed on the surface of the diaphragm over the resistors. After metallization, the individual elements are separated from the wafer, usually along with a surrounding thicker rim portion. These elements can then be mounted on appropriate substrates and connected to appropriate circuitry for the sensing application intended.
The webs or diaphragms in the wafer are extremely thin, as for example about 0.001 inch. Since the metallization requires several steps, the wafer is subjected to considerable handling after the webs or diaphragms are formed. As a result of mishandling, the webs or diaphragms can break, producing a lower yield in satisfactory discrete elements obtained from the wafer.
In view of the foregoing, it would be better to complete the devices first and then form the webs or diaphragms. However, heretofore the completed devices could not be satisfactorily masked while the wafer backside was being etched. Apparently, metallization steps, and perhaps oxide steps, could not be satisfactorily covered with reasonable thicknesses of a maskant. The maskant typically is silicon nitride, and must be stripped before the device can be used. Hence, thick coatings of it are not desirable. Techniques have been proposed for smoothing out sharp contours on a surface prior to application of a silicon nitride coating. However, they require several layers, thick underlayers, etc., and are therefore not especially desirable. We have found a way to provide a particularly effective yet readily strippable silicon nitride masking layer without resorting to complex or expensive surface treatments or coatings. It is effective enough to permit complete formation of the semiconductive device, including metallization, on the wafer front side, and then etching of the wafer backside. Yet the maskant is readily strippable.
It is hypothesized that enhanced etchant attack of the plasma nitride at the metal steps is due to internal stresses developed in the masking film in conforming to the contour of the steps. Therefore, it is the belief of the inventors that the role of the plasma oxide is one of stress relief. This belief is supported by three pieces of experimental evidence. First, plasma oxide does not tend to smooth or round the contour of the step; rather, it tends to replicate the step. Second, plasma oxide is not an effective barrier to the particular etchant used. Its etch rate in the cavity etch solution is four times that of plasma nitride. Third, stress measurements on bare silicon wafers suggest that plasma oxide has a low Young's modulus (i.e., is compliant). It is instructive to note in this connection that, while a 10,000-15,000 A layer of plasma nitride alone cannot effectively halt etching at the metal steps, simply inserting a 2000 A layer of plasma oxide under the same thickness plasma nitride does effect good masking at the metal steps.